Field of the Invention
The present invention relates in general to a method of fabricating three-dimensionally integrated circuits. In particular, the invention relates to a method of fabricating a thin, free-standing semiconductor device layer, in which a plurality of via holes extend from the devices and/or from metallisation layers to a surface of the thin, free-standing semiconductor device layer. The free-standing semiconductor device layer and individual chips obtained therefrom are then used to fabricate a three-dimensionally integrated circuit.
Three-dimensional integration, i.e. vertical interconnection of devices fabricated by planar technology is becoming increasingly important as higher package densities and switching rates may be obtained as compared to two-dimensional systems. Current methods available in practice or in the literature for vertical interconnection for very large scale integrated (VLSI) devices are, however, relatively complex. The VLSI chips must have some through-wafer structures for vertical (backside) interconnect and backside contact and must be thinned to an appropriate thickness for good electrical performance (low vertical interconnect resistance) and good thermal control (minimal thermal mass of the stacked silicon). The final thickness of the vertically integrated chips is also important in end products where total IC volume and not just density in x and y is a key differentiator such as in hand held and mobile applications.
In a first step of a method for making a three-dimensionally integrated circuit, it is necessary to fabricate thin chips containing fully processed semiconductor devices and interconnection openings leading from the devices to one surface of the thin chips. There are methods in the literature or available from vendors for thinning wafers after full integration. For example, the methods as proposed by the company Tru-Si Technologies (see literature and advertisements from Tru-Si Technologies, an equipment vendor) involve grinding and a special type of plasma etch for the thinning of the entire wafer. The special plasma etch has a relatively slow etch rate and the equipment is relatively expensive.
Finally, wafers thinner than 300 xcexcm (for 200 mm wafers) start to present major handling challenges due to bowing. However, in the three-dimensionally stacked chip application, the final thickness should be under 100 xcexcm and preferably no thicker than required by the depths of the junctions plus the required thickness of underlying substrate required for the active circuits to be stacked. For example, for a 64M DRAM with deep trench capacitors and with metal-, metal silicide- or doped polysilicon-filled trenches as a vertical interconnect, the thickness of the finished chip for 3-D integration should be in the range of 15-20 xcexcm. The thickness of the chip determines the length of the vertical interconnect. Thicker chips therefore result in increased difficulty in processing and filling the interconnect via holes and an increased resistance of the vertical interconnects. However, for VLSI devices without these trench capacitors or deep junctions, the chips could be thinner and the vertical interconnects easier to be processed.
It is quite difficult to thin a starting wafer from its initially full thickness (approximately 750 xcexcm for 200 mm wafers) to  less than 100 xcexcm with good uniformity and without damage. U.S. Pat. No. 5,563,084, which is incorporated herein by reference, discloses a method of making a three-dimensional integrated circuit. The method includes providing a first substrate that at a first surface is provided with at least one fully processed device plane containing a plurality of independent devices or circuits in a side-by-side configuration, wherein the devices or circuits of a plurality of device planes form a device stack. A second substrate is provided which at one surface is provided with at least one fully processed device plane containing a plurality of independent devices or circuits in a side-by-side configuration, wherein the devices and circuits of a plurality of device planes form a device stack. The devices, the device stacks or the circuits having been tested to distinguish between functioning and defective devices, device stacks or circuits. One surface of the second substrate is connected to an auxiliary substrate. The second substrate is thinned or reduced from a surface opposite the main surface. The auxiliary substrate and the devices connected thereto are separated into individual chips respectively containing functioning or defective devices, device stacks or circuits. The chips containing the functioning devices, the device stacks or the circuits are aligned and attached in a side-by-side relationship on the first side of the first substrate and the auxiliary substrate is then removed. The moats created between individual chips as a result of their aligning and attaching are planarized and simultaneously with, or subsequently to, the attaching of the chips, providing electrical contacts between the devices, the device stacks or the circuits of the attached chips and the devices, device stacks and circuits of the first substrate. In a preferred embodiment, the second device substrate is shown to be made from a normal silicon wafer. It is also disclosed that the second substrate can be made of a silicon-on-insulator (SOI) substrate. In this case, it is mentioned that when thinning or reducing the second substrate instead of thinning the upper substrate down to close to the device layers, the substrate below the oxide layer of the SOI substrate may be removed.
A similar method is disclosed in German Patent DE 198 13 239 C1. It also states that the substrate to be reduced and thinned may be an SOI substrate. Moreover, it teaches that before thinning of the substrate the via holes should be formed through the oxide layer and the thinning of the substrate should be terminated when the oxide layer is reached.
The methods as disclosed in the two aforementioned patents are disadvantageous as the via holes and thus the vertical interconnections are relatively long as they must be formed through the device layer and the oxide layer formed under the device layer. It is therefore difficult to fabricate vertical interconnects which contain a sufficiently low resistance to electrically connect devices in adjacent device planes. Moreover, due to the length and aspect ratio of the via holes in the state of the art, it is difficult to deposit the electrically conducting material in a reliable manner.
It is accordingly an object of the invention to provide a method for fabricating a thin, free-standing semiconductor device layer and for making a three-dimensionally integrated circuit which overcomes the above-mentioned disadvantages of the prior art method devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a thin, free-standing device semiconductor layer. The method includes providing a semiconductor specimen having a semiconductor substrate, a buried insulation layer formed in the semiconductor substrate, and a semiconductor device layer disposed on the buried insulation layer and defining a first surface of the semiconductor specimen. The semiconductor device layer has a plurality of independent devices and metallization layers disposed therein. The semiconductor substrate extends from the buried insulation layer to a second surface of the semiconductor specimen opposite the first surface. The semiconductor device layer has a plurality of via holes formed therein and each extends to the buried insulation layer from one of the independent devices and the metallization layers. A thickness of the semiconductor substrate is reduced from the second surface by performing the steps of etching the semiconductor substrate down to the buried insulation layer with the buried insulation layer functioning as an etch stop layer; and etching the buried insulation layer down to the semiconductor device layer with the semiconductor device layer functioning as a further etch stop layer.
It is therefore an object of the present invention to provide a thin, free-standing semiconductor device layer containing via holes or vertical interconnects. The method is capable of providing device layers with a reduced thickness as compared to the state of the art and also of precisely controlling the thickness of the device layer. In particular, the thin, free-standing semiconductor device layer is formed from a semiconductor specimen provided at one of its surfaces with the semiconductor device layer having the plurality of independent devices disposed therein. The buried insulation layer are disposed below the semiconductor device layer. The semiconductor substrate extends from the buried insulation layer to a surface opposite the one surface and a plurality of via holes extend from the devices and/or from metallisation layers to the buried insulation layer. The via holes may be isolated laterally from the substrate layer by a thin conformal layer of a dielectric material and are filled with an electrically conducting material. In this manner, the thickness of the free-standing semiconductor device layer can be controlled in a precise and reliable manner. In particular, it is intended by the method of the invention that the length of the via holes are reduced, so that the vertical interconnects have a low resistivity and may be processed in an easy and reliable manner. It is a further object of the present invention to provide a method of making a three-dimensionally integrated circuit by making use of thin semiconductor device layers as obtained from the inventive method.
An important teaching of the present invention therefore is that when using a so-called SOI (silicon-on-insulator) substrate or, in a more general term, a semiconductor-on-insulator substrate, the via holes should be formed only until the insulation layer, in particular the oxide layer, and to remove the insulation layer when reducing and thinning the substrate. The removal of the insulation layer and the use of the insulation layer and the device layer as etch stop layers in the two etching steps allows the fabrication of a thin, free-standing semiconductor device layer with precise control of thickness. Also the length of the via holes and thus the length of the vertical interconnects can be limited to the thickness of the semiconductor device layer, so that the via holes can be easily filled with electrically conducting material and vertical interconnects with sufficiently low resistivity can be obtained.
The semiconductor specimen, in particular the SOI substrate, as used in the inventive method can be prepared by different methods. According to one method the buried insulation layer is generated by implanting ions of the insulation layer material into the semiconductor specimen. In another method, the semiconductor specimen is fabricated by the well-known wafer bonding, wherein two semiconductor wafers having insulation layers on one of their respective surfaces are provided and bonded together at their respective insulation layers and the semiconductor layer of one of the wafers is thinned to become the said semiconductor device layer. After-wards devices are processed in the semiconductor device layer.
In order to make the insulation layer and the semiconductor device layer function as etch stop layers, the etching conditions are set such that etching selectivities of more than 10, in particular 20 to 50, between the respective material to be etched and the respective etch stop layer material are set. For example, the etchant of the semiconductor material, in particular in case of silicon, is formed of KOH or TMAH. The etchant of the buried insulation layer, in particular in case of SiO2, may then be formed of HF. After removing the SiO2, a final selective silicon etch can be used to recess the device layer silicon so that the conductor filled vias form raised features on the backside for subsequent contact in the stacking assembly process.
Before performing either of the etching steps, a mechanical grinding step to partially thin the semiconductor substrate can be performed.
When reducing the thickness of the semiconductor substrate, a portion of the semiconductor substrate, in particular a ring like edge portion may be masked by a masking layer and not reduced in thickness. This avoids the necessity of connecting an auxiliary substrate to the surface at the side of the device layer as disclosed in the above mentioned U.S. Pat. No. 5,563,084. However, in case that the semiconductor substrate should be reduced on its entire diameter an auxiliary substrate must be connected to the surface of the semiconductor specimen for stability and handling reasons.
Alternatively, the device wafer could be partially sawn from the front: side, mounted on tape on the dicing ring and subsequently processed through wet etches for bulk silicon and buried oxide layer removal. The materials of the ring and tape must withstand the chemical etches. In this way, following the oxide etch the thinned chips are ready for removing from the tape and attaching to the other substrate to form the 3-D assembly.
In accordance with an added mode of the invention, there are the steps of filling the via holes with an electrically conducting material and coating walls of the via holes with an insulating layer before filling the via holes.
In accordance with another mode of the invention, there is the step of opening the insulating layer at a bottom of the via holes anisotropically before filling in the via holes with the electrically conducting material.
The present invention also discloses a method of making a three-dimensionally integrated circuit, including the steps of providing a first substrate provided at a surface thereof with a first device layer having a plurality of independent devices (step A), fabricating a thin, free-standing semiconductor device layer according to the above described inventive method with a semiconductor specimen as a second substrate (step B), separating the devices in the semiconductor device layer of the second substrate into individual chips (step C), and mounting the chips on the first surface of the first substrate (step D). The electrical interconnections between the devices of the mounted chips and the devices in the first device layer can be formed afterwards by depositing an electrically conducting material in the via holes. However, this can also be accomplished before the stacking of the chips, for example immediately after forming of the via holes.
This method is a chip to wafer stacking method. With respect to details of steps A to D reference is made herewith to the state of the art, in particular to the U.S. Pat. No. 5,563,084 and the description given therein from column 3, line 46 to column 4, line 67, which is incorporated herein by reference.
A further method of making a three-dimensionally integrated circuit, which may be called chip to chip stacking method, includes the steps of: fabricating a first thin, free-standing semiconductor device layer according to the above described inventive method with a first semiconductor specimen as the substrate (step A), separating the devices in the semiconductor device layer of the first semiconductor specimen into individual first chips (step B), fabricating a second thin, free-standing semiconductor device layer according to the above described inventive method with a second semiconductor specimen as the substrate (step C), separating the devices in the semiconductor device layer of the second semiconductor specimen into individual second chips (Step D), mounting the first chips on the second chips (step E), and, if necessary, stacking further chips on the first or second chips until a desired stack height is achieved (step F).
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a thin, free-standing semiconductor device layer and for making a threes dimensionally integrated circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.